1. Field of the Invention
The present invention relates to a clock generator circuit for recording and reproduction of data, and more particularly to a clock generator circuit for generating a clock for the recording and reproduction of data in a sampled format system. The present invention also relates to a synchronizing signal detection method in the sampled format system and a phase comparator circuit suited for use in the generation of the clock.
2. Description of Background Information
On an optical disk such as, for example, one called a DRAW (Direct Read After Write) disk, there are recorded servo bytes as shown in FIG. 1. Each sector of the optical disk is made up of 48 servo blocks, and each servo block is formed of two bytes of servo bytes and 16 bytes of data bytes disposed in succession thereto. A servo byte is formed of two wobbled pits and one clock pit, the wobbled pits being disposed on left and right sides of the track center. When the information detecting point of the pickup (the light spot for detecting information) traces the center of the track, reductions in the quantity of light at the left and right wobbled pits become equal. However, when the tracing position is shifted to the left or right, the reductions in the quantity of the light becomes different depending upon the direction and magnitude of the shifted amount. Therefore, a tracking error signal can be generated from the difference between the reductions (the difference between levels of RF signals) at two positions and this tracking error signal is maintained during the period of the succeeding data byte.
The pairs of wobbled pits are arranged such that their spacings change between longer and shorter ones every 16 tracks. By detecting the change in the spacing, it is possible, even in a high-speed search mode to count the number of tracks correctly (16-track counting). Further, the distance D between the wobbled pit located in the rear and a clock bit is set to be a particular distance which will not appear in the data bytes. Therefore, the distance D can be detected as a synchronizing signal. Various timing signals are generated based upon the detected synchronizing signal. A clock is generated according to a detected signal of the clock pits. The mirror portion having the distance D is designated as a focus area wherefrom a focus error signal is detected, and which is maintained during the period of the succeeding data byte.
When, for example, a 5-inch DRAW disk with servo bytes recorded thereon is rotated at 1800 rpm, the edges generated in the RF signal by the clock pits has a repetition frequency of 41 28 KHz.
A clock generator circuit for generating a clock for reproducing the data recorded on such a DRAW disk in succession to the servo bytes, is shown in FIG. 2.
Referring to FIG. 2, an RF signal obtained from the disk (not shown) by a pickup 1 is supplied, after being amplified by a head amplifier 2, to a differentiating edge detector circuit 3. The differentiating edge detector circuit 8 is adapted to differentiate the RF signal for detecting edges in the signal and to output an edge pulse signal a formed of a train of pulses corresponding to the edges. This edge pulse signal a outputted from the differentiating edge detector circuit 3 is supplied to a synchronizing signal detector circuit 4 and also to one input terminal of an AND (logical product) gate 5. The sync detector circuit 4 is supplied with a reproduced clock from a PLL (Phase Locked Loop) circuit generally denoted at 6. The sync detector circuit 4 is adapted to measure the spacing between two successive pulses in the edge pulse a by, for example, counting the reproduced clock pulses during that interval and to generate a sync signal detection signal b When the obtained measurement value becomes equal to a predetermined value. The sync signal detection signal b is supplied to a gate pulse generator circuit 7. The gate pulse generator circuit 7 is adapted to generate a clock gate pulse c having a width corresponding to a predetermined length of time at the time point when a predetermined period of time has elapsed after the sync signal detection signal b was outputted according to the reproduced clock e from the PLL circuit 6. The clock gate pulse c outputted from the gate pulse generator circuit 7 is supplied to the other input terminal of the AND gate 5.
An output d of the AND gate 5 is supplied to a phase comparator circuit 8 of the PLL circuit 6. The phase comparator circuit 8 compares the phases of the output of the AND gate 5 and output of a frequency divider circuit and supplies the result of the phase comparison to a low-pass filter (hereinafter, to be called LPF) 10. The signal smoothed by the LPF 10 is supplied to a voltage-controlled oscillator (hereinafter, referred to as VCO) 11 as a control signal therefor. From the VCO 11, the reproduced clock e, (for example, at 11.1456 MHz) at the phase corresponding to the control voltage, is output. The reproduced clock e whose frequency then divided by 270 in the frequency divider circuit 9 is supplied to the phase comparator circuit 8 as a signal at 41.28 KHz.
This PLL circuit 6 is extracted as FIG. 3, and the circuit portion which generates the clock data shown in FIG. 3 is extracted as FIG. 4.
With the above described arrangement, as the light spot of the pickup 1 traces the servo byte, the level of the RF signal is lowered to the level where there are the pits, and therefore, the edge pulse a corresponding to the positions of the pits as shown in FIG. 5(a) is output from the differentiating edge detector circuit 3. When the pulse spacing of the edge pulse a becomes equal to the distance D, the sync signal detection signal b is output from the sync detector circuit 4. With reference to this sync signal detection signal b, the gate pulse c as shown in FIG. 5(b) for gating the clock edge pulse generated correspondingly to the clock pit is output from the gate pulse generator circuit 7. As the edge pulse a and the gate pulse c are supplied to the AND gate 5, only a clock edge pulse d corresponding to the clock pit as shown in FIG. 5(c) is separated and supplied to the phase comparator circuit 8 of the PLL circuit 6. As a result, the reproduced clock e at, for example 11.1456 MHz in synchronism with the clock edge pulse d, is generated by the pLL circuit 6.
Now, if a 5-inch DRAW disk is rotated at 1800 rpm, the repetition frequency of the clock pits (clock edge pulses) becomes 41.28 KHz. When the pulse width of the pulse train of the clock edge pulses is made to be a half clock (approximately 45 nanoseconds), its spectrum becomes such as that shown in FIG. 6, that is, an arrangement of discrete energy distributions at intervals of a sampling frequency of 41.28 KHz in preceding and following the clock frequency 11.1456 MHz is obtained. If the pulse widths are varied, the spectrum becomes such as that shown in FIG. 7.
In the conventional clock generator circuit of FIG. 2, since the phase comparison of input signals at the same frequency is performed in the phase comparator circuit 8, there is no danger of mis-locking the signal onto a spectrum of 11.1456 MHz.+-.41.28 N MHz (N is an integer). However, since the accuracy of the phase comparator circuit 8 is 1/270, there is a problem of increased jitters in the clock. Besides, since the detection of the synchronizing signal is performed according to the reproduced clock output from the PLL circuit 6, and further, since the gate pulse for selecting the clock edge pulse to be supplied to the PLL circuit 6 is generated according to the aforesaid synchronizing signal, detection of the synchronizing signal cannot be performed in a stable manner at the time of starting up and a considerable time is taken before the PLL circuit 6 locks, and thus, there is a problem that a stable startup is unachievable.
In addition, since the phase comparison is made with the output of divided frequency from the frequency divider circuit 9, the sensitivity of the phase is lowered to 1/270 and becomes ineffective against any shift of 10 frequency due to drift or the like in the voltage-controlled oscillator circuit 11, and therefore, there is a disadvantage that the relative phase between the clock and the clock data tends to be shifted due to change in temperature or the like.
When the 5-inch DRAW disk with the servo bytes recorded thereon is rotated at 1800 rpm as mentioned before, the edge information of the clock pit is detected at a repetition frequency of 41.28 KHz. Since the edge information of such a signal is only of a single edge, it cannot be compared in phase with a reference signal in the same way as ordinary continuous signals or burst signals continuing for a certain length of time.
In a servo byte region of an optical disk of the sampled format system, there are previously provided, as pre-pits, pits for tracking and pits acting as a synchronizing signal. Of these, the synchronizing signal is formed of a first byte of 8 ch (channel) pits and a second byte of 12 ch pits and the distance between the two is made to be 19 ch clock. Since the data are made to be smaller than 18 ch clock, the pits at the distance of 19 ch clock are detected as the synchronizing signal.
FIG. 8 is a block diagram showing a prior art synchronizing signal detection apparatus. An RF signal (FIG. 9(a)) reproduced and output from an optical disk not shown) is differentiated and an edge pulse (FIG. 9(b)) corresponding to the pre-pits is thereby generated. The edge pulse is input to a counter 12. Upon loading of the edge pulse in the counter 12, counting of a clock input thereto is started after the value of the count made up to that time has been reset. A window decoder 13 outputs a window pulse during the interval from the point when the count value of the counter 12 has become 18 (=19-1) to the point when it exceeds 20 (=19+1). When the 12 ch edge pulse is input at the time point when 19 ch clock period has elapsed after the 8 ch edge pulse was input, an AND gate 14 is rendered conductive and a sync signal detection signal is output.
In the case where the distance between two edge pulses is shorter than 19 ch clock, the counter 12 is loaded again upon receipt of the second edge pulse and the count value is reset. And, in the case where the distance is longer than 19 ch clock, an overflow signal is output from the window decoder 13 and the counting operation of the counter 12 is inhibited. Then, the counter 12 is loaded again when the next edge pulse is input thereto. Thus, the sync signal detection signal is not outputed when the distance is deferent from the synchronizing signal.
Since the conventional apparatus detects the synchronizing signal in the described manner, there is a disadvantage that the apparatus becomes unable to detect the synchronizing signal when, for example, a pulse due to noises, defects, or the like is produced between the two edge pulses constituting the synchronizing signal as typically illustrated in FIG. 9(c) and (d).